1. Field of the Invention
This invention relates to electronic device fabrication and more particularly to electronic device fabrication involving silicon.
2. Art Background
In most electronic components, such as integrated circuits, lateral separation is produced between regions of essentially single crystal silicon, i.e., silicon having less than a total of 10.sup.8 cm.sup.-2 defects, e.g., linear and planar defects such as dislocations or stacking faults, respectively. This separation is accomplished by interposing between the single crystal silicon regions, a region of electrically insulating material having a thickness approximately equal to the depth of the active regions of the single crystal materials being separated. (The active region is that portion of the single crystal silicon which is modified to contain electronic device structures. The active region is typically 1 .mu.m thick for nominal voltage devices.) In this manner, transistors or other devices formed in one single crystal region, i.e., one active region, are electrically isolated and are prevented from interacting with devices in a second active region.
However, for some significant applications the use of lateral isolation alone is not sufficient. For example, in some instances, the voltage employed in operation is often large enough to cause interaction between separate active regions. This interaction occurs by the penetration of charge carriers below one active region through the underlying substrate, across the substrate under the lateral isolation region, and up into the second active region. To prevent such undesirable electrical interaction between two active regions, vertical electrical isolation, in addition to lateral isolation, is employed. Vertical isolation is provided by underlying some, or most commonly all, of the single crystal silicon regions with a region of electrically insulating material. By this expedient, interaction between active regions even at high voltages is avoided.
Vertical isolation is also advantageously used in devices operating at nominal voltages where enhanced reliability is desirable. The additional insulating material that provides vertical isolation also prevents electron-hole pairs formed in the underlying substrate by thermal processes or by ionizing radiation from migrating to an active region and, therefore, introducing errors in the processing of information by the electronic devices in this region. Additionally, the vertical isolation reduces capacitance and, thus, allows faster device operation.
A variety of processes have been employed to produce a component having both lateral and vertical isolation. For example, a dielectric isolation process is described by K. E. Bean and W. R. Runyon, Journal of The Electrochemical Society, 124(1), 5C (1977). This process involves the use of a silicon substrate having a very low defect density. The silicon substrate is coated with an insulating material, such as silicon oxide, 3, and holes, 5, are formed in the oxide by conventional techniques, e.g., photolithography followed by chemical etching. Grooves, 7, are then etched in the exposed portions of the silicon underlying the holes in the dielectric material. These grooves, 7, are epitaxially coated with a layer of N.sup.+ silicon, 8. The n.sup.+ silicon is, in turn, coated with an insulator, 9, such as silicon oxide. The insulator is once again, in turn, coated with a layer of polysilicon, 10. The structure produced is denominated 1F in FIG. 1. The entire structure is then inverted, the silicon substrate is ground off until the structure shown at 1G is obtained. In this structure, the remaining high quality silicon is denoted by 12, insulating layers are indicated by 14 and 15, and polysilicon is indicated by 16. Thus, the final structure has single crystal silicon, 12, on an electrically insulating material.
Although this dielectric vertical isolation process has been used, it has certain shortcomings. During the processing, as the silicon oxide layer, 9, is grown, an extreme amount of compressive stress develops in the apex area, 17, of the silicon oxide layer, 9. This stress exerts a concomitant force on the adjacent single crystal silicon, 12, which results in extensive defect formation. Thus, the quality of the single crystal silicon region is significantly degraded.
Other attempts to produce a vertically isolated region of single crystal silicon have involved the use of porous silicon. (See Yoshinobu and Sunohara, Journal of the Electrochemical Society: Solid-State Science and Technology, 124(2), 285 (1977) for a description of porous silicon and its manufacture.) For example, in a representative procedure described by Imai in Solid-State Electronics, 24, 159 (1981), islands, 21 in FIG. 2, of n-type single crystal silicon are produced in a p-type silicon substrate by conventional techniques such as ion implantation. The substrate is then treated electrolytically in an aqueous HF solution under conditions which convert p-type silicon to porous silicon but leave n-type silicon essentially untouched. The porous silicon formation starts at the surface, 23, and progresses as shown at 2B in FIG. 2, until the porous silicon formation fronts join to produce the structures shown at 2C. The porous silicon typically is formed to a depth greater than half the lateral span, 24, of the n-type island--typical are 15 .mu.m lateral spans and approximately 8 .mu.m depths of porous silicon. The porous silicon is then oxidized to form a silicon oxide insulating region by subjecting the porous silicon to a temperature of about 950 degrees C. for 400 minutes in a wet oxygen ambient. Since the silicon oxide region extends vertically into the substrate to a substantial depth, vertical isolation is achieved. However, when the porous silicon region is formed, the current density during the electrolytic process at the edges, 26, of the n-type region is significantly greater than the current density in the central area, 27, of the porous silicon between n-type islands. The non-uniformity in current density produces an associated spatial non-uniformity in the density of the porous silicon. (See Arita and Sunohara supra.) When the resulting porous silicon is oxidized, the denser regions, 28 and 29, swell while the less dense regions, 30, collapse. This swelling in one region and contraction in another causes significant strain in the adjacent single crystal silicon with its attendant problems.